The implementation of other gates using only NOR gate is as shown:
Logic Gates |
Min. number of NOR Gate |
Min. number of NAND Gate |
NOT |
1 |
1 |
AND |
3 |
2 |
OR |
2 |
3 |
EX-OR |
5 |
4 |
EXNOR |
4 |
5 |
NAND |
4 |
1 |
NOR |
1 |
4 |
Half-Adder |
5 |
5 |
Half-Subtractor |
5 |
5 |
Full-Adder |
9 |
9 |
Full-Subtractor |
9 |
9 |
The output of logic circuit given below represents _______ gate.
\(Q = \overline {AB} \)
Output expression Q is equivalent to NAND gate.
Important Points
NAND GATE
Symbol:
Truth Table:
Input A |
Input B |
Output \(Y = \overline {AB}\) |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
Output Equation: \(Y = \overline {A.B} = \overline A + \overline B\)
Key Points:
1) If A is always High, the output is the inverted value of the other input B, i.e. B̅
2) The output is low only when both the inputs are high
3) It is a universal gate
XOR GATE
Symbol:
Truth Table:
Input A |
Input B |
Output Y = A ⊕ B |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
Output Equation: \(Y = {\bf{A}} \oplus {\bf{B}} = \bar AB + A\bar B\)
Key Points:
1) The output is low or '0' when both the inputs are the same. Hence XOR gate can be used to know whether two digital inputs are identical.
2) The output is high when both the inputs are different.
3) It is also called stair case switch.
4) It is mostly used in parity generation & detection.
5) 4 NAND & 5 NOR logic gates required for realization of XOR gate .
XNOR Gate:
Symbol:
Truth Table:
Input A |
Input B |
Output \(Y={\overline{A\oplus B}}\) |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
Output Equation: \(Y={\overline{A\oplus B}}\)
Key Points:
1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.
2) The output is low when both the inputs are different.
3) The output is high when both the inputs are the same.
4) XNOR gate produces an output only when the two inputs are same.
The figure below shows the IEEE/ANSI symbols alongside the traditional symbols for the basic gates:
The output Y of the logic circuit given below is:-
XOR GATE
Symbol:
Truth Table:
Input A |
Input B |
Output Y = A ⊕ B |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
Output Equation: \(Y = {\bf{A}} \oplus {\bf{B}} = \bar AB + A \bar B\)
Key Points:
1) If B is always High, the output is the inverted value of the other input A, i.e. A̅.
1) The output is low when both the inputs are the same.
2) The output is high when both the inputs are different.
Explanation:
\(Y = {\bf{\bar X}} \oplus {\bf{X}} = \bar{\bar X} X+\bar X \bar X\)
\(Y = XX+\bar X \bar X\)
\(Y = X+\bar X \)
Y = 1
Name |
AND Form |
OR Form |
Identity law |
1.A=A |
0+A=A |
Null Law |
0.A=0 |
1+A=1 |
Idempotent Law |
A.A=A |
A+A=A |
Inverse Law |
AA’=0 |
A+A’=1 |
Commutative Law |
AB=BA |
A+B=B+A |
Associative Law |
(AB)C |
(A+B)+C = A+(B+C) |
Distributive Law |
A+BC=(A+B)(A+C) |
A(B+C)=AB+AC |
Absorption Law |
A(A+B)=A |
A+AB=A |
De Morgan’s Law |
(AB)’=A’+B’ |
(A+B)’=A’B’ |
EX-NOR Gate:
Symbol:
Truth Table:
Input A |
Input B |
Output Y = A ⨀ B |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
From the truth table, the output is one when both A and B are equal logic.
The Boolean equation of output can be written as:
Output = A B + A̅ B̅
Output Equation: Y = A ⨀ B
Key Points:
1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.
2) The output is low when both the inputs are different.
3) The output is high when both the inputs are the same.
4) XNOR gate produces an output only when the two inputs are the same.
Concept:
Name of Law |
AND Law |
OR Law |
Identity Law |
1 ∙ A = A |
0 + A = A |
Null Law |
0 ∙ A = 0 |
1 + A = 1 |
Inverse Law |
A ∙ A = A |
A + A = A |
Idempotent Law |
A ∙ A’ = 0 |
A + A’ = 1 |
Associative Law |
A ∙ B = B ∙ A |
A + B = B + A |
Distributive Law |
(A ∙ B) C = A (B ∙ C) |
(A + B) + C = A + (B + C) |
Absorption Law |
A (A + B) = A |
A + A ∙ B = A |
De Morgan Law |
(A ∙ B)’ = A’ + B’ |
(A + B)’ = A’ ∙ B’ |
Calculation:
Given,
F = A B + AB'C + AB'C'
F = AB + AB’ (C + C’)
F = AB + AB’
F = A (B + B’)
F = A
Hence, '0' gate is required for that expression
Concept:
3 variable K-maps:
Calculation:
Given Boolean expression is,
F = AB + AC̅ + BC
= A B C̅ + A B C + A B̅ C̅ + A B C̅ + A B C + A̅ B C
\(= \sum \left( {{m_6},\;{m_7},\;{m_4},\;{m_6},\;{m_7},\;{m_3}} \right)\)
\(= \sum \left( {{m_3},\;{m_4},\;{m_6},\;{m_7}} \right)\)
F = BC + AC̅
The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if the outputs of all the gates whose outputs are shorted are HIGH.
The number of distinct values of 𝑋_{3 }𝑋_{2 }𝑋_{1 }𝑋_{0} (out of the 16 possible values) that give 𝑌 = 1 is _______.B = X_{0 }. (X_{1} ⊕ X_{2})
\(A = \overline {{X_0}}\)
Case 1
When X_{0} = 0
A = 1, B = 0, C = 0
output Y = C + X_{3} = X_{3}
Case 2
When X_{0} = 1
A = 0 and C = 0
output Y = C + X_{3} = X_{3}
Thus in both cases.
output Y = X_{3}
output Y will be 1, when X_{3} = 1
Favourable cases:
x_{3} |
x_{2} |
x_{1} |
x_{0} |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
Thus there are 8 favourable cases for output Y = 1
After the simplification, we can redraw the given logic circuit as
So that, Y = X.A̅
Y = (X) (0)
Y = 0
Now, Z = X + Y
Z = (A + B) + (0)
Z = (1 + 1) + (0)
∴ Z = 1
The output of the logic gate in the figure is given as
The given gate is an XNOR gate. NOR gate is an OR gate followed by a NOT gate.
Symbol:
Truth Table:
Input A |
Input B |
Output \(Y={\overline{A\oplus B}}\) |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
Output Equation: \(Y={\overline{A\oplus B}}\)
Key Points:
1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.
1) The output is low when both the inputs are different.
2) The output is high when both the inputs are the same.
The figure below shows the IEEE/ANSI symbols alongside the traditional symbols for the basic gates:
\(Z = \overline {\overline {A.B} \;.\;\overline {C.D\;} \;.\;\overline {EF} }\)
\(Z = \overline {\overline {A.B\;} \; + \;\overline {C.D\;} + \;\overline {EF\;} }\)
Z = AB + CD + EF
Determine the logical operation of the given circuit.
Concept:
In AND logic gate:
The output state of a digital logic AND gate only returns “LOW” again when ANY of its inputs are at a logic level “0”.
In other words for a logic AND gate, any LOW input will give a LOW output.
The logic or Boolean expression is given by Y = A.B
If both A and B are true, then Q is true.
The given logic circuit is
X_{1} = A.B
X_{2} = X_{1}.C = A.B.C
X = X_{2}.D = A.B.C.D = ABCD
Important Points
Buffer (Y = A)
NOT Gate (Y = A̅ )
OR Gate (Y = A+B)
NAND Gate (\(\) \(Y = \overline {AB} \))
NOR Gate (\(Y = \overline {A + B} \))
Ex-OR Gate (Y = A ⊕ B )
EX-NOR Gate (Y = A ⊙ B)
7432:
7400:
7486:
7408:
Note:
74 LS 32 → Quad 2-Input OR Gate
74 HC 00 → Quad 2-Input NAND Gate
74 HC 86 → Quad 2-Input EXOR Gate
74 HC 08 → Quad 2-Input AND Gate
Which of the following logic gates provides output as 1 when both inputs are different?
XOR GATE
Symbol:
Truth Table:
Input A |
Input B |
Output Y = A ⊕ B |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
Output Equation: \(Y = {\bf{A}} \oplus {\bf{B}} = \bar AB + A\bar B\)
Key Points:
1) The output is low or '0' when both the inputs are the same. Hence XOR gate can be used to know whether two digital inputs are identical.
2) The output is high or '1' when both the inputs are different.
3) It is also called stair case switch.
4) It is mostly used in parity generation & detection.
5) 4 NAND & 5 NOR logic gates required for realization of XOR gate .
For Ex - NOT, AND and OR gate realization using NAND gate is as shown:
The number of 2-input NAND gates required to implement a 2-input XOR gate is 4.
Similarly, the number of 2-input NOR gates required to implement a 2-input XNOR gate is 4.
Logic Gates |
Min. number of NOR Gate |
Min. number of NAND Gate |
NOT |
1 |
1 |
AND |
3 |
2 |
OR |
2 |
3 |
EX-OR |
5 |
4 |
EXNOR |
4 |
5 |
NAND |
4 |
1 |
NOR |
1 |
4 |
Half-Adder |
5 |
5 |
Half-Subtractor |
5 |
5 |
Full-Adder |
9 |
9 |
Full-Subtractor |
9 |
9 |
What will be the fundamental frequency for the following circuit if each inverter delay is 100 nsec?
Concept:
Propagation Delay:
The propagation delay, or gate delay, is the length of time that starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change.
T = 2n Tpd
Here 2 is multiplied with the propagation delay when logic gates are connected in feedback.
T is the time period of the output
n is the number of logic gates
Tpd is the propagation delay of one gate
Calculation:
Given,
n = 3 as there are three gates with feedback
Tpd = 100 nsec
T = 2 × 3 × 10^{-7}
T= 6 × 10-7
Fundamental Frequency is given by f
\(f=\frac{1}{T}\)
\(f=\frac{1}{6 \ × \ 10^{-7}}\)
f = 1.67 × 10^{6}
f = 1.67 MHz
The given image represents which logic gate?
Explanation:
The given Gate represents NOR gate:
The truth table for NOR gate:
A |
B |
\(\overline {A + B} = Q\) |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
Hence option (1) is the correct answer.
Which of the following logical operations could be computed by the given network?
Concept:
In Digital Electronics, Logic 1 means High and Logic 0 means low.
Whenever in diode, if 1 is applied to anode and 0 to cathode then Diode acts as a short circuit i.e. ON.
And if 0 is applied to anode and 1 to cathode Diode acts as open circuit i.e. OFF.
Explanation:
The given logic circuit is
For different logic of A and B,4 cases are there and according to that logic of C will vary.
Case 1
When A is logic 0 and B is logic 0
Then the logic of C will be 0.
Case 2
When A is logic 0 and B is logic 1
Then the logic of C will be 1.
Case 3
When A is logic 1 and B is logic 0
Then the logic of C will be 1.
Case 4
When A is logic 1 and B is logic 1
Then the logic of C will be 1.
According to Result, we make a table
A |
B |
C |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
This Table is of Logic OR gate.
∴ C = A + B
Important Points
Logic Circuit for AND gate is C = AB
A |
B |
C |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |